Imec released its updated semiconductor technology roadmap at ITF World 2026 this week, and the dates are more specific than prior cycles: complementary FETs (CFETs) enter commercial production around 2033, and 2D semiconductor channel materials (molybdenum disulfide and its atomic-layer-thick cousins) replace silicon channels around 2041. These are not aspirational projections. They are de-risking milestones that determine when EDA vendors, PDK developers, and process integration teams need to have working solutions ready.
The CFET stacks PMOS and NMOS transistors vertically instead of side by side, roughly halving the area of standard cell logic. Intel, Samsung, and TSMC all have prototype CFET devices in the lab. Samsung will detail a 6-layer nanosheet CFET at the IEEE VLSI Symposium in June, the most layers demonstrated to date. The key open question imec names is not whether CFETs work, but how to build them: the preferred integration path requires bonding two wafers together so that each transistor type is built on a separate substrate and then fused, a process that introduces new contamination and alignment challenges. Imec's current research focus is on the electrical isolation between the stacked P and N transistors, which determines whether the design can actually treat them as independent devices.
For EDA and PDK teams, 2033 is close enough to plan around now. Standard cell libraries for 6-track or 5-track cell heights on FinFET nodes took 3-5 years to mature from first PDK release to production sign-off quality. CFET PDKs will not be simpler. Synopsys and Cadence have already started certifying flows on TSMC angstrom-era nodes; the teams that are not starting CFET-aware physical design research in 2026-2027 will be playing catch-up when the first commercial PDKs land. The 2041 date for 2D materials is too far out to plan around today, but the CFET window is actionable.