Imec and EV Group presented wafer-to-wafer hybrid bonding at 200nm Cu interconnect pitch at ECTC this week, with a post-bond Cu pad overlay below 40nm for 100 percent of dies across a full 300mm wafer. Previous demonstrations at this pitch range failed on yield when overlay errors compounded across the wafer edge. Sub-40nm for every die on a 300mm wafer is the production signal, not just a research signal.
The mechanism is a co-optimized process flow using SiCN as the dielectric, a controlled CMP step to achieve flat surfaces with precise Cu pad recess, and EVG's GEMINI FB bonding system for overlay accuracy. The test vehicle has four layers of routable interconnects pre-processed on each wafer before bonding, so the demonstrated yield is on a realistic multi-layer stack, not a planar test coupon. Imec is framing this as the enabling technology for CMOS 2.0 logic-to-logic tier stacking, where an SoC is partitioned into a high-drive logic layer and a high-density logic layer bonded face-to-face. That partitioning approach requires interconnect densities that only W2W hybrid bonding can provide at this pitch.
The consequence is that logic-to-logic 3D stacking is no longer a roadmap slide. The overlay accuracy and process maturity demonstrated here move it into the range where a design team can start partitioning an SoC with confidence that the bonding process will not be the yield limiter. The near-term beneficiaries are hyperscaler custom silicon programs already evaluating 3D stacking for AI accelerator dies where interconnect bandwidth between logic tiers is the constraint. The next question is when volume production tooling at 200nm pitch lands at TSMC and Samsung foundry lines. Imec's history on advanced packaging milestones is 3-5 years ahead of volume production.