Classical DRAM is running into two walls at once: voltage scaling (sub-1.5V operation degrades sensing margin in conventional capacitors) and density (2D cell arrays hit interconnect resistance limits before they hit transistor limits). Imec presented two ferroelectric memory results at VLSI 2026 that take different paths around those walls. Ferroelectric capacitors operating at approximately 1.3V with greater than 40 uC/cm^2 remnant polarization and 10^13 cycles of endurance. And a functional 5-word-line vertical stack of IGZO-based FeFETs, the first demonstrated 3D-stackable ferroelectric transistor memory architecture at that tier count.
The capacitor result is a direct DRAM substitute candidate. 1.3V operation is compatible with sub-3nm logic supply rails, and 10^13 cycles matches production DRAM endurance specs. The polarization value is high enough to maintain read margin at that voltage, which has been the primary blocker for prior low-voltage ferroelectric work. The FeFET result uses IGZO as the channel material, enabling vertical stacking without the leakage constraints that make silicon-channel FeFETs difficult to stack. The dual-gate configuration with a back-gate solves the classical FeFET weakness: slow, incomplete erase. Both approaches share a common ferroelectric material stack, which means insights from capacitor interfacial engineering carry directly into FeFET optimization. This is a unified research program, not two parallel dead ends.
The immediate audience is AI inference SoC teams evaluating embedded memory for weight buffers and activation storage. SRAM area is capped; conventional DRAM latency is a bandwidth bottleneck at proximity. Ferroelectric capacitor memory at 1.3V with 10^13 endurance is a credible embedded candidate within a 3-to-5 year PDK window, assuming production integration work starts now. DRAM vendors whose roadmaps assume conventional capacitor scaling extends comfortably past 1.5V have less time than they thought.