Intel is disclosing 18A-P details ahead of the VLSI 2026 symposium starting Sunday, and the numbers are specific enough to benchmark against TSMC. Compared to base 18A, the 18A-P node delivers 9% performance gain at the same power, 18% power reduction at the same performance, and 50% improvement in thermal conductivity. Skew corners tighten by 30%. These are node-level improvements without a density shrink, meaning IP and physical design already validated on 18A transfers to 18A-P with minimal rework.
The thermal conductivity gain is the piece that has not gotten enough attention. AI chip packaging is running into thermal limits as die power densities climb. A 50% improvement in the substrate's ability to conduct heat away from the die changes the thermal budget available to chip designers before they have to involve package-level cooling solutions. For teams designing AI inference accelerators with sustained workloads, this is a first-order constraint being moved.
Intel's foundry business is in customer acquisition mode. The base 18A already has Xeon 6+ in production. 18A-P is the node for the next wave of external customers. The direct comparison is TSMC A16, also being presented at VLSI this week. A16 uses Super Power Rail for backside power; 18A-P uses PowerVia. Both claim similar PPA gains over their predecessors. Both are targeting Q4 2026 or 2027 production. For teams evaluating foundry options beyond TSMC for 2027-2028 tapeouts, VLSI 2026 is the first time full specs for both nodes are public at the same time. The answer to "can Intel foundry compete with TSMC at leading-edge" now has enough data to make a real engineering decision, not a guess.