Intel's Rio Rancho, New Mexico facility is now operating at 8x the industry-standard reticle limit for chiplet assembly, with a roadmap to 12x by 2028. This is not a feature announcement. It is Intel telling potential foundry customers the specific size constraint it can remove: the reticle limit has been the hard ceiling on monolithic die area for decades, and exceeding it requires either multi-die packaging or accepting area-limited designs. Intel is doing the multi-die packaging in the US, using Foveros 3D stacking plus EMIB and the new EMIB-T variant that routes power directly through the bridge rather than around it.
EMIB-T is the specific addition that matters for AI hardware. High-bandwidth memory and AI accelerator tiles generate enormous power-delivery challenges at package scale. Routing power through the interconnect bridge instead of through substrate traces reduces IR drop and the signal integrity tax that comes with dense HBM configurations. The 2,700 people at Rio Rancho now have a tool in their process that the rest of the US advanced-packaging supply chain does not yet have at volume.
The constraint being removed for chiplet designers who need domestic manufacturing is access, not capability. TSMC's CoWoS is dominant but backlogged for years and outside the US. TSMC's Arizona packaging is not yet at the same scale. Intel Foundry has had the technology; Rio Rancho is the announcement that it is the production address for customers with supply-chain or defense requirements that mandate US soil. If Intel can hold the 12x roadmap through 2028, every AI accelerator design that needs scale-up interconnect bandwidth and domestic assembly has a credible alternative to waiting in a TSMC queue.