Itera just emerged from stealth with reconfigurable PCB prototyping: liquid-metal tracks and vias that rewire on demand. The target is the prototype spin cycle: 2-6 weeks per board iteration, 6-10 physical boards discarded per design, IP shipped overseas for fabrication. Itera's claim is under 60 seconds to reconfigure, unlimited iterations without manufacturing, and remote probing of any internal circuit node. The boards run at U.S. testing centers; design files stay on your side.
The constraint being removed is not routing speed. It is routing iteration being the pacing item for hardware bringup. Every embedded engineer who has waited three weeks for a revised prototype because of a single net placement error knows what that tax costs. Itera is attacking the loop where a design change that takes 10 minutes in CAD takes three weeks to physically validate. If the reconfiguration capability holds at production signal integrity, it also changes what "prototype" means: instead of a fixed artifact you validate once, it becomes a continuous experiment platform.
The open questions are fidelity and frequency. Liquid-metal tracks may not maintain SI/PI characteristics equivalent to etched copper at high speeds, and the remote probing model introduces latency that matters for real-time debug. Itera is waitlist-only, so the production performance envelope is unproven. That said, if even half the capability lands, the traditional PCB board house is no longer the relevant comparison for early-stage hardware validation. The five-board prototype budget and the 45-day board spin cycle are both targets for disruption.