Safety-critical real-time systems on DDR5 have a hidden timing hazard that nobody measured. The PRAC (Per-Row-Activation-Counter) RowHammer countermeasure, standardized for DDR5, throttles DRAM access when high activation rates are detected on a row. That throttle introduces variable latency. Real-time systems are certified against WCET bounds. If PRAC fires during execution, actual task runtime exceeds the WCET analysis, and the timing contract is broken.
The RTSS 2026 paper goes further. PRAC-induced throttling is not just a worst-case scenario that might occur in practice; it is exploitable. A carefully crafted memory access pattern from an unprivileged co-located workload can trigger PRAC throttling in a victim real-time task, inducing timing violations on demand. No kernel access required. No hardware modification. The countermeasure intended to protect memory integrity becomes the mechanism for attacking timing integrity. The prior work evaluating PRAC used average-case performance metrics, which are the wrong metric for any system where worst-case behavior is the safety contract.
Every automotive, avionics, or industrial control system that upgraded to DDR5 for the security improvements needs to re-run WCET analysis with PRAC-induced jitter in the model. WCET analysis performed under DDR4 assumptions does not transfer. Systems currently being qualified against DDR5 that were previously certified on DDR4 need re-validation before they ship. The vendors selling DDR5 as the safe upgrade path have been presenting average-case data to a market that buys on worst-case guarantees. That mismatch will cost re-spins.