Known Good Die screening was designed for a world where SoC integration happened at the package level, the die was a monolith, and reliability screening meant confirming the die functioned before assembly. That assumption fails for chiplet-based AI SoCs, where post-assembly interface stress, thermal coupling between stacked dies, and partial observability after bonding can produce failures that no pre-assembly test sees. This paper formalizes the gap and proposes a path to close it.
The formalism is called Known Good Reliable Die (KGRD) and rests on four contributions: a Bayesian risk model that maps pre-assembly telemetry to post-assembly failure probability with a quantified observability bias bound; a safety-gated disposition architecture with a provable failure probability guarantee; uncertainty-aware boundaries derived from Bayes-optimal decision theory; and a closed-loop feedback mechanism that improves the model without violating reliability constraints. A Monte Carlo study on 4,000 synthetic dies validates all four properties and confirms the safety guarantee holds across the full tested gate threshold range. The key mechanism is treating pre-assembly observability as incomplete: the model knows what it cannot see and prices the uncertainty into its disposition, rather than treating KGD as sufficient and shipping into the unknown.
The practical consequence is a test strategy question for any team assembling chiplet AI SoCs: are your pre-assembly acceptance criteria leaving a reliability gap that will show up as early field failures? As heterogeneous integration moves from research to production and chiplet stacks ship at scale, the answer is probably yes for any team that has not revisited their KGD acceptance criteria with post-assembly reliability data in the loop. The KGRD framework is the right shape for that revisit. The 12-18 month window before it shows up in production test equipment is the window to build the Bayesian model from field return data before the field return rate becomes a headline.