Lam Research opened a panel-level packaging center of excellence in Salzburg, Austria, focused on wet processing for square and rectangular substrates of varying sizes. The announcement is quiet. The constraint it addresses is not.
CoWoS, TSMC's current dominant 2.5D packaging approach, is built for round 300mm wafers. Round wafers impose a reticle-stitching limit that caps how many HBM stacks and compute die fit on a single interposer. TSMC's own roadmap pushes CoWoS to 14 reticles and 24 HBM stacks by 2029, and the equipment community knows round-wafer processing will hit a ceiling before then. Panel-level packaging uses flat rectangular substrates, the same format as PCB manufacturing, which scales to much larger areas without the reticle limit. The challenge is that panel-level wet processing, cleaning, and patterning at the precision required for chiplet interconnects does not yet have a mature equipment base. Lam's Salzburg center is building that base: wet processing recipes, equipment qualification, and process integration for panel substrates of varying sizes.
The timeline matters. AI accelerator demand is outpacing CoWoS capacity today. Every major AI chip program is looking at panel-level packaging as the post-CoWoS path. Lam Research establishing R&D infrastructure in Salzburg, near Austria's semiconductor equipment cluster and within the European Chips Act supply chain, is equipment-layer groundwork for packaging technology that will determine AI hardware density in the 2028-2031 window. Teams designing AI chips for tape-out in 2027-2028 should be tracking which foundries are qualifying panel-level processes, because the interposer format their chip is designed for may not exist yet.