Power analysis has a timing problem that most hardware teams work around rather than solve. Toggle propagation through a netlist is accurate but slow. Estimating power from RTL is fast but unreliable. LEAP, a DAC 2026 paper from Zhiyao Xie's group, closes that gap: a self-supervised graph transformer trained to simulate toggle propagation achieves 7.6x speedup over the commercial EDA tool while hitting a PR-AUC of 0.99 on toggle prediction. The key architectural move is a linear-complexity graph transformer that captures both circuit structure and logical function via purpose-built pre-training tasks, without needing labeled per-cycle simulation data to train.
The mechanism matters because it changes when power analysis can run. Today, meaningful power analysis waits for post-synthesis or post-layout netlists, which means power feedback arrives after the architectural decisions that drive power have already been locked in. LEAP-Power, the integration layer the authors build on top of LEAP, enables per-cycle power estimates from RTL toggle patterns, which means power estimation can enter the feedback loop before floorplan. For teams doing DVFS tuning, clock gating insertion, or memory power optimization, getting 7.6x faster estimates at 0.99 accuracy earlier in the flow is a qualitatively different capability, not an incremental speedup.
EDA vendors have long sold power analysis as a post-synthesis or post-layout service, priced per CPU-hour of commercial simulator access. A model that predicts the same result 7.6x faster, runs on any RTL environment, and is self-supervised (no labeled netlist data required) does not fit that licensing model. If LEAP or a successor makes it to a maintained open-source release, it will be one of the cleaner examples of ML compressing a commercial EDA capability into a pre-layout CI check. Teams evaluating ML-based power analysis should run LEAP against their current sign-off flow before the next synthesis cycle.