Logic synthesis makes PPA decisions without knowing where gates will land. Wire Load Models estimate wirelength from statistical tables, not layout. P&R inherits a netlist optimized for phantom physics and spends iterations unwinding what synthesis assumed. This is accepted as the cost of separating the two stages, and design closure schedules are padded accordingly. LevelSyn argues the separation is not fundamental -- it is a coordinate prediction problem.
The mechanism is a level-asynchronous GNN that operates on the And-Inverter Graph, capturing hierarchical logic depth and signal direction that spectral methods miss. The GNN predicts gate coordinates with enough fidelity to drive a wirelength-aware optimization engine inside Berkeley ABC. Level-aligned subgraph partitioning handles industrial-scale netlists without memory blow-up while preserving local logical dependencies. The spatial predictions feed synthesis decisions that are physically grounded before P&R, reducing the correction load on the downstream tool.
Benchmarked on the EPFL suite, LevelSyn outperforms conventional synthesis on post-route PPA. The larger claim is that synthesis and physical design are not epistemically separate stages -- they have been artificially separated by the absence of spatial information in synthesis. If those results hold at production design complexity, the teams most exposed are the ones whose design closure methodology depends on iteration rather than front-loading physical awareness. That is most teams.