Coastrnaut encoded a safety state in eight bits so that one flipped bit couldn't turn "healthy" into "tripped." Then synthesis, the step that converts hardware source into gates and registers, reduced those eight state bits to two. With the fault latch included, a nine-register protection became three registers, and a single upset could again produce the wrong state.
The optimizer followed its normal rules, recognized a finite-state machine, and replaced the two eight-bit values with a smaller encoding. Disabling that pass still let it merge bits whose behavior was identical. Coastrnaut now marks the registers so Vivado, AMD's field-programmable gate array build tool, keeps them and makes the build count all nine registers after synthesis and again after routing. A smaller count stops the build.
The fix hasn't completed a Vivado build because the developer's installation lacks the target device files, and the open Yosys flow doesn't carry these protection attributes through correctly. Teams claiming fault tolerance from source-level encoding should add a post-synthesis structural test before their next hardware build.