Version 1.3 adds three kinds of serial controller to the board's programmable chip. The design includes two asynchronous serial ports, two Serial Peripheral Interface masters, and one Inter-Integrated Circuit controller. Any of them can be assigned to the board's general-purpose pins from the Forth prompt. That turns a wiring decision that normally gets fixed in the chip design into a command a firmware developer can change while testing a peripheral.
The useful part is the ownership table behind the pin router. A serial port, pulse-width modulator, or frequency generator must claim its pins before it starts, and a conflicting request fails without changing the hardware state. The release also adds transfer-level software models plus 2,016 checks in a Verilog test bench, so the same routing rules can be exercised before a wire is moved.
The design is close to its limit, using 40 of 42 memory blocks and 6,451 of 8,064 logic elements. That makes this a practical test of the idea rather than an unlimited abstraction. Teams building small programmable-chip instruments should try the ownership pattern even if they keep fixed pin assignments, because a refused configuration is cheaper than two peripherals driving the same trace.