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SignalarXiv

MeshReduce-U Cuts AI Accelerator NoC Traffic 40% With a Compiler Pass

A compiler framework rewrites communication graphs before routing on mesh NoCs, eliminating traffic that conventional placers leave on the table, with 40% latency reduction on AI workloads.

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MeshReduce-U adds a compiler pass before NoC routing that rewrites the communication graph rather than routing the graph it was handed. The constraint it removes is one that conventional NoC mappers accept as given: that the traffic graph is fixed and optimization means finding better routes through it. It is not fixed. Associative reductions expose legal opportunities to eliminate traffic before a single route is committed, and a compiler can find them automatically.

The mechanism is a sequence of structural rewrites (coalescing colocated sources, forming local aggregation islands, blocking channels with compatible fan-in structure) followed by a deterministic route-replay model that reports schedule-derived latency and link utilization separately. Across a 20-workload neural-network benchmark, MeshReduce-U reduces mean latency 40.3%, total link usage 56.0%, and fused link usage 48.7%, improving all three metrics on every single workload. On synthetic irregular reductions, 12.3% latency and 19.7% TLU reduction. The gains are not from better placement search; they come from rewriting the communication structure so there is less traffic to route.

Teams designing spatial AI accelerators with mesh interconnects have been leaving 40% latency on the table by treating the communication graph as immutable input to the placer-router, a constraint MeshReduce-U reclassifies as a compiler problem. The teams positioned to move first are those building spatial accelerators where irregular reduction patterns (sparse attention, MoE gating, GNN aggregation) dominate the traffic mix, which in 2026 is most of the interesting AI hardware work.