minisim added an open mapper that turns register-transfer-level (RTL) hardware code into field-programmable gate array (FPGA) cells for four device families. The project checks the generated circuit four ways, including an independent equivalence proof and a real place-and-route run, so users get evidence that the mapper preserved the design.
The mapper converts logic into lookup tables, the small programmable truth tables inside an FPGA, then emits files for the nextpnr placement tool or commercial device software. Its tests compare random simulations, run the original and mapped circuits through the same testbench, ask Yosys to prove them equivalent, and route the result for two Lattice chip families. One thread and four threads must also produce byte-identical output. On the project's 128 by 128 multiplier, four threads cut mapping time from 0.95 seconds to 0.37 seconds while keeping the output unchanged.
The current limits are clear: arithmetic doesn't use carry chains, multipliers don't use dedicated signal-processing blocks, and memories become individual flip-flops. Mature vendor flows remain the better choice for production designs. minisim is already a practical reference for small designs and for testing whether a larger synthesizer changed the circuit, which is where an open, deterministic mapper can earn trust first.