Gate-level simulation is the standard checkpoint between synthesis and signoff, and hardware engineers trust it to evaluate whether clock-gating insertions actually reduce dynamic power. A paper accepted at IEEE UEMCON 2026 from Xingran Huang et al. runs that assumption on the open-source OpenMSP430 core and finds the trust is not warranted. The study compares behavioral RTL-level clock-gating insertion against synthesis-inserted clock gating across multiple strategies, then checks whether gate-level simulation tracks the actual PPA outcomes. It does not, and the authors call this out explicitly as a caveat practitioners need to account for.
The mechanism is not surprising in retrospect: clock-gating cells in standard cell libraries interact with back-annotated timing models in ways that gate-level simulation does not always capture correctly, particularly when ICGs (integrated clock gate cells) are used versus manual always-block gating. The behavioral simulation was designed for functional verification, not power-mode correctness. Using it to sign off on power reduction claims adds a validation gap that can survive all the way to tapeout. The paper ships a reproducible artifact on GitHub (openmsp430-low-power-study-full) that teams can run directly.
Any embedded team using gate-level simulation as the gate for clock-gating sign-off should treat this as a calibration check. The open-source core and full reproduction kit lower the cost of validation to hours, not a tape-out cycle. The loser here is the implicit practice of treating gate-level sim as a power oracle. It never was one.