Synopsys and TSMC demonstrated in-field monitor, test, and repair for a two-die chiplet system on a silicon interposer, using UCIe as the test transport. The shift is not in the individual DFT techniques. It is in what the test strategy is now expected to cover: not just "working at time zero" but "detecting and recovering from defects that develop in the field over the product lifetime." For AI training clusters and automotive SoCs, that is a fundamentally different design-for-test contract than the industry has historically written.
The mechanism details are worth tracking. Signal integrity monitors run parallel to the UCIe data path, sampling eye diagram openings to catch PHY degradation before it becomes a data error. ATPG patterns route from PCIe through die 1's UCIe controller to reach a hidden die 2 -- a physical-aware bridge pattern approach that cut the number of required test bridges by 95-99%. IEEE 1838 IJTAG provides the access path without needing a separate PHY interface. The combination means an engineer can load test patterns to a die that has no direct external access, run memory BiST, repair defective lanes, and record the repair in OTP -- all through in-system interfaces that are already in the package for functional reasons.
The cost structure is shifting as a result. The assumption behind ATE pricing and test time allocation has been that manufacturing test is the primary investment and field failures are warranty costs. In-system test that runs at power-on, during idle cycles, and on degradation triggers changes that accounting: test is not a phase but a capability the chip carries through its operational life. For chiplet integrators deciding between off-the-shelf UCIe IP and custom interfaces, IEEE 1838 plus UCIe health monitoring is increasingly the baseline spec, not an optional add-on.