NAS finds architectures that perform well in FP32 simulation. Hardware deployment requires quantization, and quantization reshuffles the Pareto front in ways the NAS sweep did not account for. The gap between "best NAS result" and "best deployable design" is a coordination tax paid in manual iteration. A paper from researchers at University of Patras closes that gap with a three-stage pipeline that runs from architecture search through INT4 post-training quantization to hardware mapping on CGRA4ML, without a human in the loop between stages.
The pipeline structure is: a hardware-agnostic Pareto rank surrogate filters the NAS-Bench-201 search space (all 15,625 architectures) to surface Pareto-optimal candidates under target latency and accuracy; a quantization bridge applies INT4 PTQ with Pareto-aware feedback to prune architectures that do not survive quantization intact; an evolutionary domain space exploration backend maps surviving architectures to CGRA4ML for hardware realization. The empirical finding is that an FP32-zero-shot ranking model predicts post-PTQ Pareto structure with high fidelity, which means the quantization step does not require a separate NAS sweep.
The practical implication is that teams shipping edge AI on CGRA or reconfigurable accelerators no longer need to treat NAS and hardware mapping as sequential manual decisions separated by a quantization experiment. The pipeline makes the co-design decision in one automated pass. That removes approximately one to two weeks of iteration from the embedded AI accelerator design cycle.
The open question is whether this generalizes past NAS-Bench-201 to production search spaces, which are larger and less clean. If the Pareto rank surrogate holds under real training noise and partial architecture evaluations, this becomes a standard first step in accelerator design rather than a research result. The code availability and CGRA4ML integration will determine how fast that happens.