Instruction fetching burns more than 40% of total energy in the baseline NEORV32 RISC-V core running CNN inference at 0.5V on GF22nm FDX+. This paper ships two loop cache architectures that attack that number directly. The dynamic cache detects short backward-branch loops at runtime and caches them automatically. The static cache is software-managed: the boot sequence preloads arbitrary instruction blocks into a hot-code buffer, and those blocks stay there. The static version is the story: at 83.3% instruction-fetch reduction and 35.5% total energy savings, with 0.2% SoC area overhead and no microarchitectural changes to the RISC-V pipeline. The implementation is open source on NEORV32.
The tradeoff is the software burden. Static caching requires a boot-time preload decision: the developer chooses which hot loops to cache before runtime. That is not automatic, but it is also not hard on embedded targets where the inference workload is fixed at compile time. For edge AI processors where the CNN structure is known ahead of deployment, static caching is the right instrument. No runtime detection overhead, predictable energy profile, and a payoff that compounds with CNN depth.
The reason this matters for teams shipping RISC-V edge silicon is that the energy budget on batteryless or tightly constrained nodes is often what determines deployment viability, not compute throughput. Cutting core instruction-fetch energy by a third without touching the ISA, without new hardware primitives, and without layout area cost is the kind of result that moves a product from "needs an external battery" to "runs on harvested power." If you are designing a RISC-V core for edge AI inference in the next 18 months, the static loop cache is now the baseline to beat on energy per inference.