NextSilicon announced at RISC-V Summit Europe this week that it will productize Arbel, its 10-wide superscalar RISC-V performance core, into a standalone 64-core and 128-core enterprise processor targeting AI and HPC inference, with availability projected for early 2028. Arbel was first proven inside Maverick2, NextSilicon's reconfigurable network accelerator. Moving it to a standalone server CPU is a different product bet: that RISC-V is now competitive enough on per-core performance to win datacenter socket decisions without needing a proprietary accelerator strapped alongside it.
The architecture choice matters for the builder community. Most teams designing custom silicon for AI inference in 2026 are choosing between Arm Neoverse V3/N3 and in-house cores. RISC-V has been competitive at the embedded and edge tier, but the enterprise inference tier has been Arm's by default because no open-ISA vendor had production silicon at that core count and clock. Arbel's 10-wide out-of-order microarchitecture targets the same compute density bracket as Arm's Neoverse V3. If the silicon delivers at the stated target, teams taping out custom accelerators in 2027 have a credible RISC-V option for the host processor - with no ISA licensing bill attached.
The real pressure lands on Arm's royalty model. Arm's server licensing has survived because the alternative was either in-house core development (expensive) or x86 (not competitive on power). RISC-V cores with genuine enterprise performance remove that binary. NextSilicon is not yet shipping and 2028 is a long runway, but the announcement at the RISC-V Summit changes the roadmap assumption. Teams starting datacenter silicon programs now that will tape out in 2027-2028 need to put Arbel on the shortlist. The ones that don't will explain that decision to investors when the royalty line item shows up in their unit economics.