In-memory compute for neural network training has been stuck on a device physics problem: eNVM cells (ReRAM, FeFET, PCM) drift from their programmed conductance targets under real write conditions. The standard response is post-training correction, which adds latency and partially offsets the energy advantage. NOVA takes a different approach: rather than correcting for non-ideality after the fact, it designs the training algorithm around the device's stable conductance regions from the start. The result is 15.1% average accuracy recovery across benchmark tasks under severe device asymmetry, and 33.58x energy efficiency over GPU.
The architecture is a 2D ferroelectric field-effect transistor (FeFET) accelerator with a behavioral model calibrated to real device measurements. The Non-ideality Avoidance Training (NAT) algorithm guides weight convergence toward the conductance states where FeFET writes land reliably -- essentially treating the device stability map as a constraint the optimizer must respect. This removes the iterative correction loop that other in-memory training approaches require and keeps the training path entirely on-chip.
33x energy efficiency over GPU is the number that matters, but with a boundary condition: this paper tests on standard vision and NLP benchmarks, not frontier-scale models. The immediate beneficiary is edge teams running continuous fine-tuning on fixed hardware budgets -- industrial inference nodes, embedded control systems, automotive edge processors -- where GPU training cost is a structural barrier, not a convenience issue. If the result holds on larger models, the on-chip training market looks very different from the outside in 18 months. The corrective case is that FeFET device uniformity at manufacturing scale remains unproven; 33x efficiency on a fabricated test device is not the same as 33x on a production wafer run.