Nvidia Research published HORIZON, a self-evolving agent framework that treats RTL design as repository-level code evolution. The constraint being removed is not AI assistance for chip design. It is the assumption that hardware design requires human handoffs between every iteration. HORIZON compiles design intent into a Markdown harness, runs a hands-free agent loop over an isolated git worktree, and achieves 100% benchmark completion across ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories without a human in the loop.
The mechanism matters as much as the results. Hardware design repositories have always had the shape of software repositories -- RTL files, testbenches, constraints, scripts -- but the tooling treated them as artifacts to be operated on by EDA GUIs rather than as code to be evolved in a loop. HORIZON flips that: git operations handle state management, tracing, and replay. The evaluator and acceptance predicate are executable. The agent runs the same feedback loop that a software engineer runs, except at hardware abstraction level. The paper explicitly extends prior repository-scale self-evolution work from EDA software systems to hardware-design artifacts themselves.
The benchmark numbers are clean but the researchers are honest about their scope. ChipBench, RTLLM, and Verilog-Eval are controlled proxies for the much harder problem of real chip design with timing closure, DRC, and multi-domain constraints. The meaningful signal is not "AI has solved chip design." It is that the agent paradigm -- iterate, evaluate, accept, replay -- now applies to RTL with the same infrastructure patterns used in software CI. For EDA vendors whose licensing model assumes hardware engineers are the fixed, indispensable element in the loop, this trajectory is the one to watch over the next 24 months.