openPIO now runs the same protocol tests against two versions of its input/output coprocessor: the register-transfer level (RTL) source that designers edit, and the hardened gate-level netlist that describes the cells selected for fabrication. That gives the project a direct check that its behavior survived the trip from hardware code to a manufacturable Tiny Tapeout design.
The project uses cocotb, a Python framework that drives and observes hardware simulations. A new workflow runs those tests on every change to the design, test bench, or reference model. After the chip-hardening job completes, Tiny Tapeout's gate-level test action runs the suite again on the generated netlist. Both jobs preserve waveforms and test results, so a failure has evidence an engineer can inspect instead of only a red status mark.
Gate-level simulation is slower and still cannot prove that fabricated silicon will work, but it catches a valuable class of mismatches after synthesis and physical implementation. Small chip projects should copy this setup before tapeout: keep one behavioral suite, run it early on RTL, then make the manufacturing output earn the same pass.