Two-phase clocking has been a known power optimization for decades. Teams building low-power embedded and mobile designs knew the technique would help. Almost no one used it, because implementing it without tool support was a multi-week expert effort. A paper submitted to arXiv on May 8 ships the first fully automated flow for two-phase clocking inside OpenROAD Flow Scripts, and the numbers are not subtle: 29.2% power reduction and 50% latch count reduction over the alternative implementation, plus timing closure via time borrowing on a benchmark design that failed timing with standard flip-flops.
The flow runs Yosys technology mapping and ABC retiming to convert flip-flop-based RTL into two-phase latch-based designs, then dual clock tree synthesis, two-phase correctness validation, and full physical design RTL-to-GDS. Two variants ship: clock-gated (better power) and recirculation mux. The clock-gated variant achieves the 29.2% reduction. The entire pipeline runs inside OpenROAD Flow Scripts -- open-source, no new license, no new vendor relationship. Teams already running OpenROAD can pull this in today.
EDA vendors selling "low-power flow" add-ons in the five- and six-figure annual contract range are now competing against a free open-source flow with a 29.2% power number attached. Hardware engineers have known two-phase clocking works for decades. The missing piece was never understanding -- it was the 3-4 weeks of manual implementation work that made the optimization uneconomical to attempt on any design that was not already in trouble. OpenROAD just eliminated that tax. Expect adoption in edge AI inference and battery-constrained IoT designs within 12 months as teams discover the checkbox exists.