Semiwiki published a technical breakdown of Siemens' HyperLynx DRC -- the automated rule-based electrical verification tool that addresses SI, PI, and EMI/EMC at PCB level. The core argument: manual layer-by-layer inspection does not scale to modern board densities, and point-tool simulation run only at signoff guarantees respins.
The PCB complexity problem is underappreciated in the AI hardware conversation. Everyone talks about advanced packaging and chiplets, but the boards those packages land on are also getting harder: multi-gigabit SerDes, tighter power delivery constraints, and EMI/EMC requirements that now affect almost every DDR, PCIe, and USB trace. A single missed impedance discontinuity or return path issue can require a full board spin -- months of schedule and real cost.
The HyperLynx DRC approach -- automated DRCs run continuously through the design cycle rather than as a gate at the end -- is the right architectural pattern. The practical challenge is model setup: S-parameter models, extracted 3D structures, and vendor datasheets all have to be ingested and validated before the rules mean anything. That setup cost is where teams cut corners and where the tool saves the least time on first use.
The shift-left verification argument here is essentially the same one that drove adoption of formal verification in digital IC design a decade ago. PCB is behind IC design on this curve, which means the productivity delta for teams that adopt it now is larger than it will be in five years when it is table stakes.