PCIe 7.0 doubles full-duplex throughput on an x16 link to 512 GB/s at 128 GT/s flit mode -- the bandwidth headline everyone talks about. The problem is that raw bandwidth and sustained throughput are two different things, and the gap between them is widest precisely in the AI workloads PCIe 7.0 is supposed to accelerate.
The issue is ordering. The PCIe ordering model -- strict, relaxed, ID-based -- was designed around a producer-consumer abstraction where ordering conveys semantic meaning. That made sense for decades of CPU-centric traffic. AI factory patterns (GPU collective ops, gradient reductions, sharded parameter broadcasts) are structurally different: many independent streams, statistically aggregated results, never consumed in program order. Enforcing fabric-level ordering on this traffic causes head-of-line blocking, inflates buffering requirements, and starves parallel paths -- all while physical bandwidth sits idle.
The fix is the Unordered I/O (UIO) engineering change notice, first introduced in PCIe 6.1 and carried into 7.0. UIO shifts producer-consumer ordering responsibility from the fabric to the endpoints, declaring at the wire level that ordering is semantically irrelevant for flagged traffic classes. For AI factory workloads, this is the right abstraction: endpoints that do not need ordering guarantees should not pay the fabric cost for them.
The detail worth noting: UIO is an ECN -- an engineering change notice, not a clean-sheet redesign. It is layered onto an existing spec rather than replacing the ordering model. That means correct use requires endpoints and switches to negotiate and signal UIO capability. System designers integrating PCIe 7.0 into AI accelerator clusters need to verify that every component in the path correctly implements and exposes this capability -- not just that the spec version is right.