PCI-SIG released PCIe 8.0 Draft 0.5 on schedule, setting 256 GT/s and 1 TB/s bi-directional bandwidth as the floor for AI accelerator interconnect in 2028. Hardware teams designing AI server platforms today now have a known upper bound on what the bus will deliver for the next silicon generation.
The draft doubles raw transfer rates from PCIe 7.0's 128 GT/s using PAM4 signaling and FLIT encoding, reaching 1 TB/s bi-directional on a x16 link. The spec formalizes CopprLink copper cable support alongside optical alternatives, which means PCIe 8.0 platform designs are no longer constrained to rigid board-trace topologies. SI engineers working on PCIe 7.0 bring-up are beginning prototype work at 256 GT/s now; the 2028 final spec gives them a defined target for signal integrity validation before the wave of 2nm AI accelerator tape-outs lands in customer hands.
PCIe 8.0 delivers 8x the bandwidth of PCIe 5.0 in a backwards-compatible envelope. That ratio forces a decision for AI system architects choosing fabric topology in 2026: any interconnect architecture designed around PCIe 5.0 as the ceiling will need a re-spin for the accelerator generation shipping in late 2028. Teams building custom ASIC tapeouts on 2nm nodes scheduled for 2026-2027 need PCIe 8.0 PHY IP qualification timelines on their radar now, not in 2027.