Every AI chip placement paper since 2021 benchmarks against HPWL (half-perimeter wirelength). PPAPlace runs a label fidelity study across ten circuits at four flow stages and finds that HPWL correlates near-zero with post-route WNS and TNS. The authors then evaluate six published AI placers: all six regressed PPA relative to the hierarchical baseline. The constraint being removed is not placement quality -- it is the false confidence that HPWL scores meant anything about timing.
The mechanism is straightforward once you see it. Placement tools push macros to minimize wirelength because wirelength is cheap to compute and differentiable. Post-route timing depends on congestion, cell sizing, buffer insertion, and layer assignment -- none of which HPWL captures. The same fidelity gap exists at pre-route timing, which the paper also tests. The only proxy that reflects final timing rankings is post-global-routing, which is expensive but available. PPAPlace trains a dual-stream surrogate (graph attention over the netlist, spatial convolution over the placement grid) on post-global-routing labels, then backpropagates WNS and TNS gradients end-to-end to cell coordinates during placement.
The practical implication: EDA teams evaluating AI placers by HPWL are comparing tools on a dimension that does not correlate with the metric they actually ship against. If PPAPlace's approach generalizes -- and ICCAD 2026 acceptance is a reasonable signal that it does -- then the right label for placement surrogates is post-global-routing, and any benchmark suite still using HPWL is measuring the wrong thing. Mid-market fabless teams spending engineering cycles tuning AI placers against HPWL targets should reassess what they are actually optimizing. The AI EDA placement hype cycle ran five years on a broken objective.