The hardware prefetching research field has been optimizing against a proxy metric that does not track endpoint behavior. A new matched-control study separates the admission gate from the predictor and finds the gate matters more. A 257-parameter online MLP is indistinguishable from a gated stride predictor on random traffic and slower on most regular streams.
The experiment applies the same confidence gate to both a neural prefetcher and a classical stride predictor across 20 SPEC CPU2017 programs in native ChampSim. The gate removes 35% of prefetches and improves accuracy from 11% to 15%. The load-bearing number: DRAM reads change by only 0.07%. The proxy metric that the field uses to evaluate prefetchers (DRAM read bandwidth) is functionally inert in this study while the accuracy and prefetch-count numbers move significantly. The paper also proves that gate-closed execution reproduces the no-prefetch baseline exactly, giving system architects a clean isolation method for separating prefetcher effects from baseline behavior.
A decade of ML-for-microarchitecture papers have reported benchmark wins on prefetching with evaluations that conflate the predictor and the admission policy. The correct comparison requires matching controls. Chip architects evaluating neural prefetcher IP should audit which component is actually earning the measured improvement before committing the die area. For the research community, the finding is harder to ignore: if DRAM reads change 0.07% while accuracy moves 4 percentage points, DRAM reads are not the right metric for prefetching, and papers reporting DRAM-read improvements are measuring the wrong thing.