Skip to content
hw.dev
hw.dev/signal/pulse-sequencer-8192-dds-rows-hardware-check-2026
SignalPulse Sequencer

A Bench Test Proves 8,192 Frequency Rows Reach the Hardware

A changed frequency pattern proves that a fast table load reached the instrument instead of reusing stale state.

Thesis connection

A bench check now distinguishes a real hardware update from an old value that merely looks correct.

#fpga#testing#verification#tools
Read Original

Pulse Sequencer loaded 8,192 frequency rows into its direct digital synthesis hardware in 0.05 seconds, then stepped through the table from a field-programmable gate array. The useful part is how the developer proved the result wasn't stale: the test changed its default frequencies from 50, 100, 150, and 200 megahertz to 60, 110, 160, and 210 megahertz before running the bench check.

Two paths reached the same hardware. In one, the host wrote five rows and advanced them through trigger commands. In the other, the host loaded all 8,192 rows and a timing signal on the board advanced the sequence. The instrument produced all four requested frequencies and then turned its radio-frequency output off on the fifth step, while the run also confirmed the byte order used on the wire.

Changing the pattern is a small but strong test design choice because an old table can't accidentally pass. The next useful check is to power-cycle the board between load and playback and preserve the measured output with the test log; that would separate correct transport from persistence or startup behavior.