Skip to content
hw.dev
hw.dev/signal/quicklogic-efpga-12lp-post-silicon-change-2026
SignalQuickLogic

QuickLogic Adds a Patch Panel Inside 12LP SoCs

QuickLogic's 12LP eFPGA IP lets SoC teams reserve a small region for post-silicon changes instead of turning every missed requirement into a respin.

Thesis connection

A programmable region inside an SoC moves some validation findings from the next tapeout into a bitstream update, compressing the loop from discovered defect to tested fix.

#fpga#eda#semiconductor#tools
Read Original

QuickLogic is giving GlobalFoundries 12LP and 12LP+ SoCs a controlled escape hatch after tapeout. Its new eFPGA IP reserves programmable logic inside the chip, so a late interface change, accelerator experiment, or hardware bug does not automatically become a mask revision. The constraint being removed is the assumption that every logic decision is permanent at signoff.

The IP is available in 10x10 and 20x20 logic-cell arrays, with automated generation of Verilog wrappers, floorplanning, and timing constraints. QuickLogic also exposes a CLI and supports Python and Tcl scripting. That packaging matters more than the fabric itself: an eFPGA block only compresses development if integration and bitstream generation fit into the existing RTL and CI flow rather than becoming a specialist side project.

The trade is area, power, and another verification boundary in exchange for post-silicon options. Teams planning a 12LP tapeout should prototype one likely ECO in the smallest array before committing. If that exercise takes more than two engineer-weeks, the integration flow is not ready to insure a multimillion-dollar respin.

Back to Signal