Analog in-memory computing ships with a deployment problem that digital hardware does not have: every physical chip is wrong in its own way. Programming noise, limited-resolution converters, and broken cells mean that picking which accelerator from a pool to run in production has historically been guesswork dressed as engineering. RACE-AIMC replaces the guesswork with statistics: offline, it studies a pool of physical AIMC chips, selects the single best one for a given energy budget, and computes a mathematically exact upper bound on how often that chip will be wrong when it answers.
The online path runs only the selected accelerator. A lightweight check at inference time decides whether to accept its answer or defer to a digital fallback. In simulation across noisy weight mappings and multiple test runs, every certified error bound stayed under the 10% target (mean 7.83% +/- 0.89%), with 70.88% of inputs answered by the analog chip directly. That selective deployment model cuts modeled energy use 69.02% relative to always running the full accelerator pool, while matching the accuracy of a clean digital baseline.
The shift here is from "we hope this chip is good enough" to "we can prove this chip meets spec with a stated false-positive rate." That is the gap between a research demo and a deployed edge product. Analog IMC has been stuck at the demo stage partly because the validation story was thin: if you cannot certify that a chip's output stays within bounds, you cannot sign off on a safety-critical or SLA-bound deployment. RACE-AIMC gives analog IMC the same class of deployment contract that digital systems have had for decades. Teams evaluating analog accelerators for edge inference should run this framework against their chip pool before committing to silicon volume.