RadSlice added a Verilog implementation of the 64-bit base-integer RISC-V instruction set and checks it in lockstep against a reference emulator. The same core runs with 8-, 16-, and 32-bit internal slices on ChaCha20 and a CoreMark-like workload. Each configuration must agree with the reference while the project records the fixed execution cost per instruction.
Lockstep is the important choice here. The experiment changes how many bits the arithmetic hardware processes on each beat, which changes cycle count and the amount of duplicated logic. Comparing final program output could miss a wrong intermediate state that happens to cancel out. The new trace path and test bench compare the configurable hardware with one stable model instead of creating a different expected result for every width.
RadSlice is candid that its wider yield and fault-rate study is simulation built on many hypothetical parameters. The functional check is useful anyway because it separates "does this architecture execute correctly?" from "would its manufacturing assumptions hold?" The next credibility test is whether the same harness catches injected errors in memory accesses, exceptions, and control registers, where processor experiments usually become harder to compare.