Architect Labs just published Redwood, a frontier AI accelerator that went from high-level specification to verified, deployed hardware in under two weeks, with no human intervention below the specification level. The constraint being removed is not design speed as measured in CAD hours. It is the assumption that trained engineers must author every artifact between a spec and working silicon.
Two architects wrote a specification. The AI system generated the performance model, RTL, UVM environments, formal proofs, firmware, and kernels autonomously. Every block reached 95% coverage through commercial EDA tools, a proprietary formal engine, and hardware-in-the-loop validation. Specification changes were reverified and redeployed to the FPGA implementation in under 48 hours. Projected onto Samsung 8nm (the Jetson Orin Nano process class), Redwood delivers 1.75x the throughput at 1.9x lower power on the same models, a 3.4x performance-per-watt gain on measured baselines.
The paper closes with a detail worth sitting with: Qwen running on Redwood helped design next-generation Redwood. The recursive loop is closed, not as a demo but as a shipped system. The hardware-software co-design team that used to span years and dozens of engineers is now two architects and a deadline. Any silicon team that is not stress-testing agentic design flows against their current tape-out cycle has 18-24 months before a competitor shows up with a chip that was designed, verified, and revised in the time they spent on design review scheduling.