Reticle can now place, route, and configure the dedicated digital signal processing blocks inside Xilinx 7-series field-programmable gate arrays (FPGAs). Without those blocks, an open tool must build multipliers and filters from general-purpose logic. One 18-bit multiplier used 746 lookup tables and 145 storage elements before this change; Reticle now maps it to one arithmetic block, nine lookup tables, and 37 storage elements.
The stronger part is how Reticle checked the mapping. Its developers swept block settings through Vivado 2026.1, Xilinx's vendor design tool, then compared 170 generated designs with Vivado's output. Tests also cover 52 block settings, 194 register settings, and 78 sums. That work found a clock connected to the wrong network and a three-stage calculation that selected the wrong two stages, even when the generated configuration bits otherwise matched.
Reticle's developers haven't run these designs on a physical board, and their notes keep that limit visible. The next credible milestone is a board suite that exercises multiplication, accumulation, and long filter chains while comparing every output with the software model. The measured parity now supports serious evaluation. Replacing Vivado on arithmetic-heavy products will require that physical evidence across several boards and tool releases.