Reticle found that its Zynq UltraScale+ model placed every processor pin at the processor block's single nominal location, even when each signal entered the programmable fabric at a different row. On one 128-bit processor-bus design, that mistake pulled nearby logic about 142 rows away from the real connection point. The first routing pass searched 950 million nodes and took 14 minutes.
The fix follows each processor pin to the first tile where its wire enters the field-programmable gate array (FPGA), a chip whose logic and wiring can be configured after manufacturing. Reticle now gives that tile to both the placer and the router's distance estimate. The same design searched 20.5 million nodes and completed in 2.5 minutes, while a new test checks that processor pins map across the fabric instead of collapsing onto one location.
This is the kind of improvement open electronic design automation (EDA) needs: a physical claim, a failing design, and before-and-after measurements in the same commit. The remaining risk is coverage, because the test checks placement locations but can't fully catch a regression in the router's estimate. Reticle should add the node count or a bounded runtime to continuous integration once that measurement is stable enough across machines.