At the RISC-V Summit Europe 2026 in Bologna this week, Philipp Tomsich reported that both the Integrated Matrix Extension (IME) and Vector Matrix Extension (VME) specifications are converging on specification freeze, with unified LLVM-MLIR compiler support emerging alongside them. This resolves the toolchain portability problem that has kept RISC-V out of serious AI inference workloads for the past two years.
The issue has been that without a ratified matrix instruction set, every RISC-V chip targeting AI inference had to ship with vendor-specific extensions: Alibaba T-Head vectors, Nuclei DSP instructions, SiFive custom P-extensions. Each required its own LLVM backend. A model optimized for one chip had to be recompiled, retested, and often recalibrated for every other target. The result: RISC-V AI inference was stuck in single-vendor product lines with no second-source path. VME adds outer product matrix multiply accumulate instructions with configurable register file dimensions, covering data paths from 4-bit integer up to FP32, across implementation points from low-area MCUs to high-performance HPC cores. The unified LLVM-MLIR path means that compiler infrastructure being built for one conformant chip works for all of them.
When IME/VME ratification lands (the current trajectory points to late 2026), RISC-V chips targeting on-device AI will be able to use the same compiler stack as ARM or x86 targets. That creates a second-source path for edge inference deployments that currently have no alternative to Qualcomm QNN or Apple ANE. The first vendor to ship a Zephyr-compatible, IME-conformant MCU with a CMSIS-NN backend will take the embedded AI inference market the same way the original RVV cores took the vector DSP market from proprietary SIMD extensions. Budget 12 months from spec freeze to first conformant silicon in volume production.