DRAM read-disturbance mitigations have been sized against models that do not match device behavior. Luo et al. use TCAD simulations to identify exactly which parameters cause the mismatch across three metrics (bitflip directions, bitflip counts, and minimum aggressor activations to trigger an error), and deliver updated error mechanisms that match experimental data. Memory system designers now have a calibration framework, not just empirical data points that conflict with theory.
The gap mattered in practice. RowHammer and RowPress mitigations (Target Row Refresh, PRAC, and similar schemes) are sized against a threat model. If the model underestimates the number of flips or the aggressor activation threshold, the mitigation is undersized: a system that passes certification fails in the field when access patterns hit edge cases the model did not predict. The Mutlu lab (ETH Zurich) has been the reference group on RowHammer research for a decade, and this work closes the loop between the empirical observation that the model was wrong and a simulation-level explanation of why and which parameters to tune.
The immediate builder application is in characterization infrastructure. DRAM reliability testing today is largely empirical: run the access pattern, count the flips, compare against a floor. A calibrated TCAD model enables a different approach: use the model to predict which device parameters in a given DRAM lot will produce the most vulnerable cells, then target the test budget at those. That is a shift from exhaustive empirical search to model-guided verification, which is the same shift CI-native DRC made against exhaustive LVS sweeps. The teams building HBM stacks and LPDDR-attached inference hardware should be reading this paper, not waiting for the JEDEC working group to absorb it.