RISC-V Vector Extension 1.0 is in shipping silicon, and a team presenting at the ISC26 RISC-V for HPC workshop has done the first systematic benchmark across that silicon on real HPC workloads. The platforms under test: SiFive X280 (Tenstorrent Blackhole), SpacemiT X60 and X100 (K1 and K3), and T-Head C920v2 (Sophon SG2044). The benchmark suite is BLAS, FFTW, HPL, HPCG, STREAM, and FMA throughput. Comparison point: NVIDIA Grace, the current ARM64 HPC baseline.
The headline finding is directionally correct but granular: RVV 1.0 delivers significant improvement over scalar RISC-V execution, but hardware-specific implementation gaps -- not the ISA -- are the remaining limiter. Vectorization efficiency varies meaningfully across the four tested chips, which means the ISA ratification was the easy part. Compiler maturity, microarchitectural implementation quality, and memory subsystem tuning are where the gap lives now.
This is the data that teams evaluating RISC-V for edge HPC, AI inference infrastructure, and workloads where vendor-neutral silicon matters can actually use. The answer is not "RISC-V is HPC-ready" or "it isn't." It is: RVV 1.0 silicon ships, it vectorizes correctly, and the per-chip implementation gap versus ARM64 is concrete and measurable on standard HPC workloads. The first platform to close that gap on a specific workload class -- dense linear algebra, FFT-heavy signal processing, or memory-bandwidth-bound inference -- wins the deployment conversation for that class. Tenstorrent Blackhole, with SiFive X280 and RISC-V as the management core, is the most likely candidate to get there first for AI inference workloads where the surrounding accelerator architecture already differentiates.