Cadence and Samsung Foundry announced at CadenceLive 2026 that they are co-developing a silicon prototype of a physical AI chiplet platform on Samsung's SF5A (5nm) process technology. The platform uses Cadence's Chiplet Spec-to-Packaged-Parts ecosystem with pre-verified partner IP, targeting robotics, AI radar, and autonomous sensor systems. Tape-out is planned for early 2027, volume production in the second half of that year.
The mechanism worth watching is the Spec-to-Packaged-Parts framing. Chiplet design today requires teams to simultaneously manage die-to-die interface specs, packaging substrate constraints, foundry DRCs across multiple nodes, and IP integration -- each owned by a different team and managed in a different tool. Pre-verifying a set of chiplets on a known foundry process (SF5A) with a certified packaging flow collapses that coordination cost for any team building on the platform. You trade design flexibility for a faster path from architecture decision to tape-out. For physical AI edge workloads (cameras, radar, autonomous machines) where the design space is bounded and time-to-market drives everything, that tradeoff is correct.
The loser in this trajectory is the full-custom SoC for mid-volume physical AI applications. If Samsung and Cadence pre-verify a chiplet ecosystem that covers the relevant compute tiles (matrix engines, sensor front-ends) and the packaging flow is certified, then the argument for a custom monolithic SoC below a certain volume threshold collapses within two to three product generations. Contract manufacturers running their own ASIC flows on SF5A will feel this first.