Library characterization has been the invisible tax on advanced-node tapeouts for years. At 3nm and 2nm, the number of PVT corners multiplies, LVF data volumes balloon, and SPICE simulation queues stretch into weeks while taping-out teams wait. Siemens today announced Solido Characterizer, the next generation of its Solido Characterization Suite, with a 7x total throughput improvement: a 5x speedup from AI-driven LVF techniques combined with a 2x boost from LibSPICE, the first purpose-built AI-accelerated simulator for library IP. GlobalFoundries is cited as an early adopter, validating production accuracy at internal flows.
The mechanism has two layers. Solido Characterizer handles the SPICE-backed anchor simulations that every foundry requires, now faster through LibSPICE optimizing specifically for library workloads rather than treating them as general SPICE. On top of that, Solido Generator uses reinforcement learning to model the full PVT space from anchor corners, generating new Liberty views in minutes at 100x SPICE speed. The generator outputs NLDM, CCS, and LVF -- signoff-ready formats, not approximations. Solido Analytics replaces the multi-week manual verification pass with an AI outlier detection engine that can catch timing-impact errors in LVF data that rule-based checks miss. The full suite runs as an end-to-end flow inside a single product family.
The practical consequence is that library schedule delays stop being an EDA bottleneck at advanced nodes. Teams characterizing over hundreds of corners for 3nm and 2nm libraries have been running weeks-long SPICE queues that gate tapeout readiness. If characterization collapses to days, the schedule constraint moves to RTL sign-off and DRC, where it belongs. IP providers who sell characterized libraries on long-lead schedules have 12-18 months to redesign their delivery model before AI-accelerated characterization makes same-week turnaround table stakes.