Siemens shipped Tessent UltraSight, a system-wide functional monitoring and debug solution for chiplet-era SoCs. The positioning is blunt: as SoC complexity rises with generative AI workloads and multi-die architectures, silent data corruption and timing-sensitive bugs have become unreproducible at the bench and undebuggable without visibility infrastructure that was designed in from the start.
The mechanism is embedded analytics. UltraSight places functional monitors, sensors, and event trackers into the SoC fabric during design, not as a post-silicon debug patch. That means in-field captures, not just controlled test conditions. Silent data corruption in HPC and AI silicon has been a named industry problem since at least 2022 (Meta disclosed Fleetwide SDC rates publicly). The traditional Tessent toolkit covers structural test: scan chains, JTAG, built-in self-test. UltraSight extends that into the functional domain, which is where chiplet-era failures actually surface. A scan test that passes is not evidence that the system behaves correctly under a 256-layer attention head with full DDR bandwidth pressure.
The broader argument here is about test as infrastructure versus test as a phase. Scan chains were designed in 30 years ago and became mandatory IP. Functional monitoring is following the same arc, driven by chiplet complexity making the functional-structural boundary increasingly meaningless. The question for SoC teams is not whether to add observability, but whether to bolt it on post-silicon or spec it into the architecture from the first design review.
Teams cutting a new AI or HPC SoC tape-out in the next 6 months without a functional monitoring spec are accumulating a debug debt they will pay in field returns and customer escalations. UltraSight does not close that debt retroactively. The window is the next design review.