The Silinx Integrated Synthesis Environment (ISE) project measured nextpnr 1.1.1, an open place-and-route tool that assigns logic and wires inside a field-programmable gate array (FPGA), on a corpus of Spartan-3E designs. When the first router hits its effort limit, the fallback router now reaches 103.98 megahertz on the project's display example, up from 87.7 megahertz with the previous weights. On the congested secworks-sha256 design, its critical path fell from 31.041 nanoseconds to 24.979 nanoseconds.
The useful change isn't just a better routing weight. Silinx records the result in an automated test that forces the first router to stop, checks that the fallback took over, requires every signal to be routed, rejects warnings, and fails if the resulting clock falls below 95 megahertz. A tuning win that lives only in a benchmark note is easy to lose. This one now travels with the tool.
Open FPGA tooling needs more tests like this: real design corpora, timing numbers, and explicit floors for the cases that strain the router. Teams maintaining older Spartan parts can try version 1.1.1 against their own slowest design and compare both timing and run time before changing the production flow.