Silinx's open nextpnr flow now fits a video display design into 148 slices on a Spartan-3E field-programmable gate array (FPGA), a chip whose logic can be rewired after manufacturing. The previous release needed 157 slices. The original vendor packer uses 150 to 153. On this design, the open replacement produces the smallest result of the three.
The change is narrow and testable. nextpnr 0.10.0 can place a flip-flop, the circuit element that stores one bit, into an unused position beside a carry chain. It also takes a constant carry input from the chip's dedicated power site instead of spending a lookup table on it. Silinx added a small design that exercises the case, fixtures for the routed output, and a check that catches an illegal placement.
One display build doesn't establish that nextpnr wins across every Spartan design. It does set the right standard for open chip tools: name the physical change, publish the before-and-after resource count, and keep the case in the test suite so a later release can't quietly give the gain back.