TSMC controls roughly 70% of 2.5D packaging capacity through CoWoS. SK Hynix is now testing Intel's EMIB substrate technology for HBM integration. If that qualification succeeds, the AI chip supply chain has a second option for the packaging layer that has been the single-point bottleneck since CoWoS demand surged in 2023.
EMIB embeds a silicon bridge die in the substrate rather than using a large interposer across the full die field. The tradeoff versus CoWoS is real: lower package cost and better yield, but a reduced bandwidth ceiling for the widest interconnects. For ASIC-class designs like Google's TPU v8e and Meta's MTIA (both named as prospective customers in the report) that bandwidth tradeoff is acceptable. GPU-class designs with thousands of HBM lanes are a harder case. SK Hynix's interest goes beyond supply security: working EMIB-based HBM stacks would give SK Hynix a direct substrate R&D relationship and packaging reference flow that it currently lacks outside the TSMC CoWoS supply chain.
Intel Foundry picks up a revenue stream that does not depend on Intel product designs succeeding. For TSMC, a qualified EMIB alternative is not an immediate revenue threat (CoWoS capacity is still constrained) but it removes the pricing leverage that comes from being the only credible option. Hyperscalers running dual-source RFPs will know the alternative exists. TSMC has roughly 18-24 months before a production-qualified EMIB flow gives hyperscalers a credible alternative to cite in pricing negotiations.