SK hynix shipped 12-layer HBM4E samples on June 18, pulling forward a timeline it had placed in the second half of 2026. The relevant number is not the bandwidth figure. 4TB/s is what the roadmap promised. The relevant number is the 20% power efficiency improvement over HBM4 at the same 48GB-per-stack capacity.
AI training and inference throughput has been memory-bandwidth-bound, not compute-bound, for two years. HBM3E closed some of that gap but not the power-per-bandwidth ratio that constrains rack density. HBM4E at 12 layers, 16Gbps per pin, and 48GB per package gets you to 4TB/s, and the 20% power reduction means you get that bandwidth without proportionally expanding the thermal envelope. At rack scale, the thermal budget is the real constraint, not the peak bandwidth spec.
Samsung shipped HBM4E samples in late May. With SK hynix now sampling ahead of its own H2 guidance, two credible suppliers are entering the HBM4E generation concurrently. AI chip designers who have been constrained to a single HBM vendor now have competitive samples from both. The pricing leverage that comes from single-vendor dependency in HBM3E does not carry into HBM4E. Any custom silicon team planning a tape-out that lands in 2027 production should be running both vendors' HBM4E samples now, because the allocation negotiation starts with whoever qualified earliest.