SmartClock has decoded five field-programmable gate array (FPGA) designs from seven firmware images used in old Hewlett-Packard clocks. The work turns each XC3042 configuration into structural Verilog, a text description of the chip's logic and wiring, then runs it through Icarus Verilog instead of asking readers to trust a reverse-engineering diagram.
The useful part is the chain of checks. SmartClock tests its decoder against small designs built by the original Xilinx design software, compares pad assignments and logic blocks, and keeps reference traces for the Z3805A, 58503A/Z3801A, 58503B, Z3815A, and Z3816A. Its continuous integration job rebuilds those checks with pinned tools, so a decoder change that alters an observed clock behavior can fail like any other regression.
That makes old programmable logic maintainable in a way a binary archive isn't. Anyone repairing one of these clocks can now challenge a decoded connection, rerun the same simulation, and leave the next engineer a test instead of another interpretation.