The most expensive unbounded phase in SoC design is the one before synthesis: architects evaluating millions of configuration combinations against competing power, performance, area, and time-to-market objectives, with each candidate requiring manual handoff to implementation and verification teams to estimate feasibility. Defacto Technologies and CEA just shipped SoC PLANNER to early adopters, and the core claim is straightforward: give the tool your KPIs and parameter ranges, get back Pareto-optimal configurations with RTL included. No iteration loop. No cross-team ping-pong. 30-40 percent reduction in exploration time on the two use cases documented.
The architecture integrates three components. CEA's A-DECA handles automated design space exploration across the full configuration space, running multi-objective analysis to identify the Pareto frontier on area, latency, power, and energy efficiency. Defacto's SoC Compiler takes those configurations and generates the RTL directly, ready for synthesis and simulation. Innova's PDM manages the project and EDA flow coordination. The flow covers the complete upstream pre-synthesis design chain: architectural exploration through RTL generation, in a single platform. One additional metric is unique in the space: every configuration gets an eco-design footprint score, making sustainability a first-class design parameter alongside PPA rather than a post-hoc audit.
The beneficiary is the team running complex automotive, HPC, or AI SoC projects where manual exploration across millions of configurations is a multi-month activity staffed by senior architects. The loser is the current workflow, where the bottleneck between product requirements and tape-out schedule is a human expert with a spreadsheet. A 30-40 percent cycle reduction at this phase compounds through the downstream schedule. The open question is coverage: the two use cases shown (a neural network edge accelerator and an HPC SoC subsystem) are clean architecture-exploration problems. SoC PLANNER reaches early adopters now; how it handles the messy real-world IP integration constraints that dominate most production SoC projects will determine whether the headline numbers hold outside the lab.