Backside power delivery and 3D chiplet stacking are yield-limited by through-silicon via overlay: the TSV hole has to land on active front-side structures within tolerances that get harder to hit as wafer bow and thermal history accumulate across a 300mm substrate. Sony and imec's local BDI (backside dielectric isolation) module, presented at VLSI 2026 this week, changes that constraint. A self-aligned isolation step decouples TSV placement from lithographic overlay accuracy, producing sub-100nm vias with a 3x larger overlay window than conventional via-middle processing, at lower resistance and leakage.
Conventional via-middle TSVs are patterned relative to stepper alignment marks, which introduces cumulative overlay error across the wafer. The local BDI approach inserts a self-aligned dielectric isolation step that defines the TSV boundary relative to the surrounding device structures rather than an external reference mark. The TSV still gets etched and metalized, but the alignment-critical step is self-referencing. Low-resistance, low-leakage front-to-back connections at sub-100nm pitch without requiring tighter lithography is the result.
For chiplet packaging houses and SoC teams designing logic-on-DRAM stacks, TSV yield is a primary wafer cost driver. A 3x overlay improvement is large enough to move backside stacking from conservatively priced to mainstream in a per-wafer cost model. Sony's co-authorship is telling: at least one image sensor SoC roadmap is already built around this integration approach, which means the module is on a path to process qualification at a production facility, not just a research paper.