Sounio's compiler can now emit a kernel for an Alveo U250 field-programmable gate array (FPGA) through the same souc command used for its other targets. FPGA output is now a named compiler target with a test in continuous integration (CI), replacing an experiment that someone had to run through a separate script.
The new --target fpga-u250 path calls Sounio's self-hosted high-level synthesis (HLS) emitter, which turns a software function into hardware-oriented C++ for AMD's FPGA toolchain. Every change now builds the compiler, emits a dot-product kernel, and runs that output in a host C++ simulation. The test doesn't need an FPGA or a commercial tool license, so contributors can exercise the target on an ordinary CI worker.
Host simulation catches compiler regressions while they are still cheap to fix, before board access enters the schedule. Meeting timing and loading the design on the card still require the vendor tools. Sounio should add that run periodically; until then, this change establishes a useful first gate without pretending it is hardware qualification.